Although during the Fifties and Sixties magnetic core memories were the predominant storage technology for the working memory of computing systems, they were rapidly supplanted during the Seventies by the integrated circuit random access memory, both static (SRAM) and dynamic (DRAM). The advantages of these newer technologies are well known: microscopic size (contributing to higher operating speeds), miniscule power requirements (requiring dissipation of less waste heat), improved robustness and thus reliability, and manufacturing efficiencies of scale--all of which contributed to the dramatically reduced cost per bit. The disadvantages are equally well known: data volatility, reflected as continuous power dissipation in SRAMs, and as periodic data refresh in DRAMs. To address these problems, various types of non-volatile, read/write memory technologies have been developed, including electrically erasable programmable read only memory (EEPROM), of which Flash memory is, at present, the most popular. All such technologies, however, have additional disadvantages, including finite lifetimes (in terms of write cycles), and power supply requirements which challenge designers of battery powered systems.
Recently, magnetoresistive random access memory (MRAM) cells suitable for fabrication using current integrated circuit manufacturing processes have been developed for use as non-volatile storage elements. Examples of such an MRAM cell suitable for implementation in an IC are shown and described in U.S. Pat. Nos. 5,343,422, 5,917,749, and 5,920,500. A survey of current MRAM technologies and their relative advantages and disadvantages was published by R. Scheucrlein in "Magneto Resistive IC Memory Limitations and Architecture Implications", 1998 International NonVolatile Memory Technology Conference, IEEE, pp. 47-50 (1998).
In general, MRAM devices of the Magnetic Tunnel Junction (MTJ) type include a multi-layer resistor element comprised of suitable magnetic materials which change its resistance to the flow of electrical current depending upon the direction of magnetic polarization of the layers. In a memory cell, this "bit_resistor" is connected in series with a "bit_read" transistor between a common voltage supply and a "bit_read_write" conductor connected to an input of a "read" sense amplifier. A "word_write" conductor is arranged to intersect, relatively orthogonally, the bit_read_write conductor. The word_write and the bit_read_write conductors are connected to respective word_write and bit_write driver circuits which are selectively enabled such that each conductor conducts only a portion of the current necessary to switch the polarization state of the bit_resistor.
During a write operation, each of these "write" currents is individually insufficient to affect the polarization state of any bit_resistor, but, together, at the point of intersection or "coincidence", the currents are sufficient to affect the polarization state of that bit_resistor which is proximate to the intersection of the write conductors. Depending upon the present state of polarization and the relative directions of current flow in the write conductors, the bit_resistor at the coincidence point will either maintain or switch its polarization state.
During a read operation, the bit_read transistor is enabled via a respective word_read conductor, and, simultaneously, the corresponding bit_read sense amplifier is enabled to create a current path from the bit_read_write conductor to the common supply. Since the difference in the resistance value of the bit_resistor is small, the bit_read sense amp must be sufficiently sensitive to recognize the small differences in voltage drop across the bit_resistor associated with the respective polarization states. As was the case with magnetic core memories, an MRAM bit_resistor, once written, will retain its magnetic polarization state indefinitely, with no further input of power. Similarly, there appears to be no practical limit on the number of times that the polarization of the bit_resistor itself can be switched or "written".
In U.S. Pat. No. 4,064,494, a Content Addressable Memory (CAM) is disclosed in which each CAM cell is comprised of a pair of non-volatile storage devices, preferably of the non-destructive read-out (NDRO) type, such as floating-gate MNOS transistors. Although reference is made to "plated wire" ('494: col. 1, line 65), the detailed description and drawings are limited to MNOS embodiments, which require quite different write cycles than does a plated wire. As expected, no mention is made of MRAM devices, since such technology had not yet been invented. In any event, the write cycle described therein is inappropriate for an MRAM CAM, and, in general, the read, write and control circuitry are significantly different.
An object of the present invention is to provide an MRAM CAM.
In addition, the present invention is directed to suitable apparatus for practicing the method disclosed hereinafter.